Sequential Circuit
Q41.
Consider the following circuit with initial state Q0 = Q1 = 0. The D flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.Q42.
The below figure shows four D-type flip-flops connected as a shift register using a XOR gate. The initial state and three subsequent states for three clock pulses are also given.\begin{array}{|c|c|c|c|c|} \hline \text{State} & Q_{A} & Q_{B} & Q_{C} & Q_{D} \\\hline \text{Initial} & 1 & 1 & 1 & 1 \\\hline \text{After the first clock} & 0 & 1 & 1 & 1 \\\hline \text{After the second clock} & 0 & 0 & 1 & 1 \\\hline \text{After the third clock} & 0 & 0 & 0 & 1 \\\hline \end{array}The state Q_{A} Q_{B} Q_{C} Q_{D} after the fourth clock pulse isQ43.
Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation?